Path Optimization for Electrically Inspecting Printed Circuit Boards with Alignment Marks

In inspections of printed circuit boards (PCBs), a test probe has to be moved to a number of PCB wiring patterns in some order. This paper considers path optimization for minimizing a total path length of testing PCBs arrayed on a plane. Due to the miniaturization of PCBs, the procedure of “alignment” has been recently needed in order to know the exact position of each wiring pattern before each of PCB wiring patterns is electrically tested. Therefore, there is a precedence constraint that alignment marks of a wiring pattern have to be captured by a camera before a test probe is moved to the exact position of the wiring pattern. This paper shows that the problem to be solved can be formulated as a precedenceconstrained traveling salesman problem (TSP). An efficient heuristic algorithm is proposed to solve the problem with a practically reasonable time. The proposed algorithm is installed into real PCB inspection machines that have been widely sold in the world. Cost reduction effects for PCB inspection factories are discussed.